1. Technical Field
The present invention relates to a technology for processing a film to form a pattern by dry etching.
2. Related Art
In recent years, decreasing feature size is progressed in the fields of semiconductor devices, liquid crystal display units, optical devices or the like. For example, interconnect trenches patterned in an interlayer insulating film via a back-end process or gate oxide films or contact holes patterned via a front-end process are decreased in semiconductor devices. Besides, downscaling in thin film transistors (TFT), in which a voltage is applied to a liquid crystal molecule to drive thereof, are proceeded in liquid crystal display units. Besides, downscaling of optical guides or the like, which are patterned on a film or a substrate, are proceeded in optical devices.
Here, in the process of dry etching films, an influence of an irregularity created in the side surface of the formed pattern (line edge roughness, hereinafter referred to as “LER”) relatively increases, as the level of the downscaling of the pattern is progressed. In particular, when patterned lines such as interconnect trenches are formed, an influence of the LER formed on the side wall of the lines becomes a serious problem. When the LER increases, problems related to, for example, interconnect trenches in a semiconductor device, such as an increase in the electric resistance due to an electronic scattering in the interconnect side wall, an increase in the leakage current between the interconnects, a decrease in the interconnect life and the like are generated. Similarly, a scattering of electron in the thin film transistor of the liquid crystal display unit or a scattering of light in the optical guide of the optical device are also caused due to an increase of the LER to become a problem.
Various methods are known for forming interconnect trenches in semiconductor devices by a dry etching process. For example, Japanese Patent Laid-Open No. 2002-270,584 describes a technology for processing an interlayer insulating film that is provided with a multiple-layered resist structure including from the top, an overlying resist layer/an organic silicon oxide layer/an underlying organic layer deposited in sequence.
When the dry etch process is proceeded, a thickness of a resist film serving as a mask, as well as a thickness of an etching-target film exposed from the resist film, will be gradually decreased from an initial thickness. According to the investigation of the present inventors, it has been found that smaller thickness of the remained resist film remained on the surface of the etching-target film in the end time of the dry etch process causes larger LER in the side surface of the pattern formed on the etching-target film. It has been also found according to the investigation of a present inventor that larger surface roughness of the resist film during the etch process causes larger LER in the side surface of the pattern formed on the etching-target film.
As described in the above-described Japanese Patent Laid-Open No. 2002-270,584, a multiple-layered resist film exhibiting different etch selectivity for the upper and lower layers (overlying resist layer and underlying organic layer) and the middle layer (organic silicon oxide layer) are employed, so that a certain larger initial thickness of the underlying organic layer that serves as a mask for an etching-target film (an interlayer insulating film) can be ensured.
However, as described in the above-described Japanese Patent Laid-Open No. 2002-270,584, a larger LER is generated in the silicon-containing layer in a conventional process, in which a silicon-containing layer (organic silicon oxide layer) provided as a middle layer in the multiple-layered resist films is dry etched with a gaseous mixture of tetrafluoro carbon (CF4), oxygen and argon. It is clarified by the investigations of the present inventors that a generation of such LER is resulted from a reduced amount of the remained overlying resist layer and an increased surface roughness of the overlying resist layer. It is also, in turn, clarified by the investigations of the present inventors that a larger LER generated in the silicon-containing layer also causes a larger LER in the etching-target film that will be finally etched. On the other hand, a requirement for conducting a patterning process for the resist layer with an extremely higher resolution by employing an exposing apparatus is arisen in recent years, due to miniaturizations in the linewidth of the interconnect or the line intervals between the interconnects in the semiconductor device. Therefore, an initial film thickness of the resist layer is preferable to be fallen within a shallow focal depth of an exposing apparatus, and thus an initial film thickness of a resist layer is generally on a declining trend. In addition, when an etched depth in the multiple-layered resist films is increased to provide an increased ratio of length and width (aspect ratio) that is larger than a predetermined ratio, a problem of the resist film being easily collapsed is arisen. As described above, it is difficult to ensure the thickness of the remained resist film to be larger than a predetermined thickness at the end point of the dry etching process in recent years by providing sufficiently larger thickness of the resist film provided over the etching-target film.
The present invention is made according to the above-described circumstances, and thus the invention provides a processing method, which can achieve both of a highly precise dry etching process and a reduction of an LER. Further, the present invention in particular provides a method for manufacturing a semiconductor device including an operation of processing an etching-target film formed over a semiconductor substrate with an improved accuracy and a reduced LER.